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VLSI PROJECT TITLES

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VLSI
1 1fufhhkj Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions Export as PDF
2 1fufhhkj Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding Export as PDF
3 1fufhhkj Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication Export as PDF
4 1fufhhkj Fully Reused VLSI Architecture Of Fm0/Manchester Encoding Using Sols Technique For Dsrc Applications Export as PDF
5 1fufhhkj Recursive Approach to the Design of a Parallel Self-Timed Adder Export as PDF
6 1fufhhkj Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks Export as PDF
7 1fufhhkj 32 Bit×32 Bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler Export as PDF
8 1fufhhkj A Novel Realization of Reversible LFSR for its Application in Cryptography Export as PDF
9 1fufhhkj Critical-Path Analysis and Low-Complexity Implementation of the LMS Adaptive Algorithm Export as PDF
10 1fufhhkj A Methodology for Optimized Design of Secure Differential Logic Gates for DPA Resistant Circuits Export as PDF
11 1fufhhkj Novel Shared Multiplier Scheduling Scheme for Area-Efficient FFT/IFFT Processors Export as PDF
12 1fufhhkj Low-Complexity Tree Architecture for Finding the First Two Minima Export as PDF
13 1fufhhkj Design & Analysis of 16 bit RISC Processor Using low Power Pipelining Export as PDF
14 1fufhhkj An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator Export as PDF
15 1fufhhkj Design and Analysis of Approximate Compressors for Multiplication Export as PDF
16 1fufhhkj Low-Power and Area-Efficient Shift Register Using Pulsed Latches Export as PDF
17 1fufhhkj Variable Latency Speculative Han-Carlson Adder Export as PDF
18 1fufhhkj A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications Export as PDF
19 1fufhhkj Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks Export as PDF
20 1fufhhkj High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels Export as PDF
21 1fufhhkj Implementation of A High Speed Multiplier for High-Performance and Low Power Applications Export as PDF
22 1fufhhkj Parity Preserving Adder/ Subtractor using a Novel Reversible Gate Export as PDF
23 1fufhhkj Ultralow-Energy Variation-Aware Design: Adder Architecture Study Export as PDF
24 1fufhhkj Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations Export as PDF